An adjustable design for the Real Time Clock of high-end server systems
Ying‐Wen Bai, Hsiao-Chung Chen · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 2008
The method we propose in this paper shows how to use the factors which may affect the Real Time Clock circuit, like the PCB stack-up, the parasitic capacitance of the PCB layout and the equivalent capacitance of chipset and crystal. We enumerate all the factors and come out with an external load capacitor value to provide the load capacitance which the oscillator circuit actually needs that will make the RTC clock rate more accurate. The designer can then shorten the testing and verification time formerly consumed by trial and-error. Based on the method of calculating the parasitic capacitance between two parallel planes, we utilize the actual trace length and width as well as the stack-up properties. This parasitic capacitance can be developed into the load capacitance of an oscillator circuit, which will be used to improve the reliability of the traditional RTC design method.