Formal verification of an industrial system-on-a-chip
Hoon Young Choi, Myung Kyoon Yim, Jae-Young Lee, Byeong-Whee Yun, Yun-Tae Lee · 2002
This paper describes our experience and methodology used in the formal verification of an industrial embedded SOC product composed of the ARM920T processor core and 16 function modules, i.e., IPs. We employed the formal verification to verify the RTL implementation of each module. We used the model checking to make the RTL golden model and the equivalence checking to verify the following refinements. Specifically, we describe 1) the selection of a model checker and a modeling language, 2) the modeling of multiple clocks and gated clocks using the implicit clock of the model checker, 3) the translation between Verilog and the model checking language, and 4) the module verification strategy including the problem size reduction techniques. Results of applying the proposed verification strategy to our design are also covered.