Design of a flexible cryptographic hardware module
Andrew W. H. House, Howard M. Heys · 2004
Key elements of communication security include block ciphers and hash functions. Software implementations of these algorithms are relatively easy, but may not provide the speed necessary for some applications. For such applications, hardware implementations in ASIC or FPGA technology provide speed, but are difficult and time-consuming to develop. The SHERIF architecture described in this paper seeks to provide a flexible cryptographic hardware platform targeted for 0.18 /spl mu/m CMOS technology. A survey of major cryptographic algorithms was performed to identify common operations, and components to implement those operations implemented in a configurable manner. The components were finalized to facilitate data flow, and a key management solution was devised to handle the provision of subkeys. The system is fully configurable and is intended to support multiple algorithms such as AES, DES, RC6, and Camellia, as well as different modes of operation. A VHDL model of the system has been successfully simulated, and synthesis is in progress to produce area and timing information.