A network processor architecture for flexible QoS control in very high-speed line interfaces
Hideyuki Shimonishi, Tutomu Murase · 2002
We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism and enables effective header handling.