High-Performance Hardware Design and Implementation of Genetic Algorithms
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takahashi Iwamoto, Hiroto Yasuura · Studies in fuzziness and soft computing · 2001
In this chapter, we present a survival-based, steady-state GA designed for efficient implementation in hardware and the design of a pipelined genetic algorithm processor that can generate one new, evaluated chromosome per machine cycle. High performance is obtained by implementing the functions of parent selection, crossover, mutation, evaluation, and survival in hardware in such a manner that each function can be executed in a single machine cycle. When these hardware functions are connected in a linear pipeline (much the same as an assembly line), the net result is the generation a new child chromosome on each machine cycle. The key features of the survival-based, steady-state GA are low selection pressure due to random parent selection, steady-state population maintenance, and replacement of randomly discovered, lesser-fit chromosomes by more-fit offspring. A GA machine prototype is also presented, running at 1 MHz and generating one million new chromosomes per second. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.