An Efficient Memory System for Fast Block Matching Motion Estimation Algorithms
Yinghong Tian, Xiaojun Zhang, Zongsheng Lai · 2009
This paper proposes an efficient memory system (MS) for fast block matching motion estimation algorithms, which suffer from bandwidth problem and random block data access problem. One novel data-to-memory mapping algorithm is proposed to solve these problems. By data reuse and efficient memory arrangement based on Latin Square, the bandwidth can be reduced to 5.15 Mbit/s for SVGA video. To balance better between I/O Pads and bandwidth, the proposed MS uses 8 pixel data input. The proposed MS also proposes tree-type 2 to 1 multiplex shuffle networks and address offset method to reduce delay and optimize the implementation. The FPGA-base implementation can work at 227 MHz clock and meet real-time requirements in the SVGA video system with VBSME.