A high performance VLSI architecture for integer motion estimation in HEVC
Yuan Xu, Liu Jinsong, Liwei Gong, Zhi Zhang, Robert K. F. Teng · 2013
A high performance VLSI architecture for integer motion estimation (IME) in High Efficiency Video Coding (HEVC) is presented in this paper. It supports coding tree block (CTB) structure with the asymmetric motion partition (AMP) mode. The architecture contains two parallel sub-architectures to meet 1080p@30fps real-time video coding. The size L×L of CTB in the architecture is set to L=32 pixels by default, and it can be extended to L=64 and L=16 pixels. A serial mode decision module to find optimal partition mode for the architecture has also been implemented.