Implementation and evaluation of microinstruction controlled self test using a masked microinstruction scheme
Y. Nozuyama, A. Nishimura, Jun Iwamura · 2003
A masked microinstruction scheme which reduces the size of the test microprogram used for a microinstruction-controlled self-test, a type of built-in self-test, is described. Implementation of the scheme applied to a 32-b microprocessor, the TX1, is illustrated, and its efficiency is discussed. Over 95% fault coverage for data path blocks in an execution unit is achieved, and almost all related control logic is tested with about 600 steps of test microprogram in the TX1. Without the scheme, it is estimated that the equivalent test requires about 1200 steps. Applicability of the scheme to other types of microprocessors is also discussed.>