A high speed 2-D DCT/IDCT processor
Weiqi Li, D. Slawecki · 1991
Recently, a novel algorithm to compute the discrete cosine transform (DCT) and its inverse (IDCT) was derived by W. Li (1991). Based on this algorithm, a high-speed 8*8 2-D DCT/IDCT processor chip was designed. In the present work, the algorithm is briefly outlined; the chip architecture is presented; and some circuit design issues are discussed. The chip measures 7.9*9.2 mm/sup 2/. It is designed using the MOSIS 2- mu m SCMOS technology. It takes 16-b inputs, uses 16-b internal memory for coefficients and data, and generates 16-b outputs. A single input line determines if the chip computes the DCT or the IDCT. The chip is highly pipelined with a latency of 135 cycles and a throughput of 55 MHz, which is equivalent to computing 880 million multiplies and 770 million adds per second.>