Built-In-Test Self-Verification
M.A. Ramirez · 2005
This paper presents various techniques to be used in the development of a Built-In-Test (BIT) design with provisions for BIT self-verification. These techniques, consisting of "forced failures" and designing BIT circuits with known failure modes, enable a BIT hardware failure to be automatically detected by the equipment's BIT processor. The "forced failure" technique requires faults to be simulated in the equipment and the corresponding BIT circuitry status to be evaluated against expected results. Designing to known failure modes, the other technique, requires BIT circuits to be designed in such a way that a BIT failure can be detected by evaluating circuit status signals.