Interface finite-state machines: definition, minimization, and decomposition
Ajay J. Daga, William P. Birmingham · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1997
There is a well-recognized need for accurate timing verification tools that account for the functional behavior of component interfaces, and thereby do not traverse false combinational and sequential paths. Such tools, however, are susceptible to an exponential increase in task complexity as the circuit size and functional complexity of components increase. The viability of accurate timing verifiers hinges on their ability to efficiently analyze the smallest subset of circuit behaviors, while verifying the timing characteristics of the overall space of behaviors. This paper presents theoretical results that address this issue for the timing verification of interacting FSMs.