Prototype implementation of a highly parallel dataflow machine EM-4
Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi · 2002
The paper presents the implementation of the EM-4 prototype and reports initial performance evaluation. The EM-4 is a highly parallel computer whose design objectives are: to develop a feasible parallel computer with more than 1000 processing elements (PEs); and to pursue efficiency by improving dataflow architectures. Key features of the EM-4 are: (1) a strongly connected arc dataflow model; (2) a Multiple-RISC concept; (3) a dataflow single chip processor EMC-R and (4) a versatile interconnection network with extra facilities. As a first step the EM-4 prototype was implemented with 80 PEs. The EM-4 prototype has been fully operational since May 1990, with peak performance of 1 GIPS and peak network performance of 14.63 GB/s. It has performed 824 MIPS in the calculation of pi .>