Technology-dependent transformations for low-power synthesis
Rajendran Panda, Farid N. Najm · 1997
We propose a methodology for applying gate-level logictransformations to optimize power in digital circuits.Statisticallysimulated switching information, gate delays,signal arrival patterns, and signal probabilities are consideredin reducing the switching activity-capacitance products.Power reduction up to 45.4% (acerage 12.4%) is achieved,with considerable improvements in area and delay, in pre-optimizedbenchamarks.Also the effect of transformationson the random pattern testability of the circuits is studied.