Overscaling-friendly timing speculation architectures
John Sartori, Rakesh Kumar · 2010
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (BTWC) design approaches based on timing speculation (TS) have recently gained ground as an alternative to traditional designs by allowing processors to be designed for the average case and still maintain high yields.