A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications
Chi-Cheng Ju, Yung-Chang Chang, Chia-Yun Cheng, Chih‐Ming Wang, Hue-Min Lin, Chun-Chia Chen, Fred Chiu, Sheng-Jen Wang · 2011
In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS [email protected], H.264 [email protected], VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates 415K logic gates and 682Kbits embeded SRAM in 65nm single-poly seven-metal CMOS process with area of 2.47mm2. AVS video decoding of full 1920×1088 high-definition sequences at 60 frames per second is achieved at 166MHz clock frequency with power dissipation of 41.3mW at 1.0V supply voltage.