Video chip set for data rate compression by filtering and DPCM coding
B. Zehner, Hans Jürgen Mattausch, F. Matthiesen, Matthias Schoebinger, R. Tielert, Heinrich Klar, K. H. Moehrmann · 2003
Low-cost transmission of digital color TV signals for ISDN needs a data reduction to reduce the required channel bandwidth. A CMOS chip set performing a data rate compression from 140 Mb/s to 34 Mb/s is presented. It consists of a digital filter of sixth order switchable to horizontal or vertical filtering, an adjustable delay line, and a DPCM codec with a two-dimensional prediction algorithm and an adaptive quantizer characteristic. A set of experimental chips has been realized to demonstrate the feasibility of compact low-cost system components and to explore the potential of advanced CMOS technologies. Fully functional first silicon in 1.5- mu m CMOS technology was obtained. The achieved performance data guarantee correct function even under worst-case conditions.>