Functional Test Generation for Sequential Circuits
Josia Jacob, Vishwani D. Agrawal · 2005
We propose a method of generating tests for finite state machines (FSMs) from the same functional description that is used for logic synthesis. The faults are modeled as growth and disappearance faults in the cubical description (or personality matrix) of the irredundant combinational part of the FSM. For combinational logic alone, test vectors for these faults are eficiently derived using a cube-based method previously developed for programmable logic arrays (PLAs). It is shown that these tests provide a 100% coverage of single stuck type faults in any irredundant twolevel implementation and in the multi-level implementation obtained through testability preserving transformations. To derive tests for the sequential circuit, we represent it as an iterative array of the combinational logic whose personality matrix is modified according to the fault. A test for a growth or disappearance fault now consists of a state justification sequence, a test vector for the combinational logic and a fault propagation sequence. The cube-based PLA algorithm is extended to obtain the entire test sequence. The results on synthesis benchmark circuits show that almost 100% stuck type fault coverage can be obtained with this technique.