Architectural exploration using Verilog-based power estimation
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan · 1997
We describe an architectural design space exploration methodologythat minimizes the energy dissipation of digital circuits.The centerpiece of our methodology is a Verilog-based power estimationtool, Pythia, that blends the accuracy of low-level circuitsimulators such as powermill with the speed of high level powerestimators geared to design exploration. Pythia takes into accountvoltage-dependent capacitive nonlinearities and supports runtimeadaptation of supply voltage. It employs a hybrid modelingaproach in which low-level simulation of logic gates and flip-flopscan be combined with high level macromodels for memory structureswhere the energy per access is not as sensitive to input datastatistics. The speed and accuracy of Pythia has enabled a detailedcase study of two different approaches for the computation of theInverse Discrete Cosine Transform, an integral component of theMPEG video coding algorithm. One approach uses conventionalmethods and the other exploits signal statistics to dynamically minimizethe average number of operations required and the operatingsupply voltage.