Nonlinear DSP coprocessor cell-one cycle chip
V.K. Jain, Lei Lin · 2002
This paper presents a high-speed nonlinear coprocessor cell for computation of elementary functions. Several elementary functions are typically needed in systolic arrays for signal and image processing algorithms. With our approach, all of the desired elementary functions can be incorporated on a single cell. Furthermore, a new result can be obtained every clock cycle (with a pipelining delay of three clock cycles). A 24 bit version and a 16 bit version-both employing second order interpolation and very small ROM tables-are presented. Characteristics of the 16 bit chip, fabricated in 2.0 micron CMOS technology, are discussed in detail. As an application example, a parallel architecture for CT image reconstruction for a Fan Beam CT System is presented.