Removing JTAG bottlenecks in system interconnect test
Hong-Shin Jun, Sung Kyu Chung, Sanghyeon Baeg · 2005
This work presents a new methodology that removes JTAG bottlenecks in system interconnect test. JTAG test has a limitation by targeting only low-speed testing. But, the system interconnect test requires the test to be run at system clock speed through the cluster of the network and also needs to diagnose the skew and delay characteristics of the cluster. Resolving the synchronization issue between a high-speed pattern clock and TCK, the proposed technique enables high frequency interconnection testing, cluster testing, and delay testing. Experimental results with test vehicles show that the test technique can be used with complex interconnections including differential signal lines, AC coupling, latency, and optical signal interconnections.