Finding good counter-examples to aid design verification
Görschwin Fey, Rolf Drechsler · 2003
Today up to 80 % of the design costs for integrated circuits are due to verification. Verification tools guarantee completeness if equivalence of two designs or a property for a design are proven. In the other case usually only one counter-example is produced. Then debugging has to be carried out to locate the design error. This paper investigates, how debugging can benefit from using more than one counter-example generated by the verification tool. The problem of finding useful counterexamples is theoretically analyzed and proven to be difficult. Heuristics are introduced and their quality is underlined by experimental results. Guidelines how to generate counterexamples are extracted from one of these heuristics. 1.