The Design of a Low-Power Asynchronous DES Coprocessor for Sensor Network Encryption
Yijun Liu, Pinghua Chen, Guobo Xie, Zhusong Liu, Zhenkun Li · 2008
Sensor network nodes have a very tight power budget and the power efficiency is the biggest design concern in sensor network circuits. A general-purpose processor (e.g. an ARM processor) is not efficient to execute encryption algorithms because it has no special instructions to support encryption operations, for example very often-used permutation operations. In the paper, we propose a low-power ASIC encryption coprocessor for sensor network nodes. A DES algorithm is used because the algorithm does not include power-hungry and complex mathematic operations, such as multiplication, division and addition. An asynchronous logic style is used to design the coprocessor. With an asynchronous controller, a global clock is not necessary when idle, resulting in zero standby dynamic power. Using the DES coprocessor, the power consumed by encryption can be saved by 4 orders of magnitude than a pure software calculation.