Architecture of the Scalable Communications Core's Network on Chip
D.A. llitzky, Jeffrey D. Hoffman, Anthony Chun, Brando Perez Esparza · IEEE Micro · 2007
The SCC is a flexible and energy-and area-efficient baseband processor for concurrent multiple wireless protocols. Its architecture consists of coarse grained, heterogeneous, programmable accelerators connected via a packet-based, 3-ary 2-cube network on chip. The NOC supports goals of flexibility, scalability, and extensibility, and it meets stringent latency and throughput requirements.