A built-in self-testing approach for minimizing hardware overhead
S. Chiu, C. Papachristou · 2002
A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques.>