Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, Mikhail Grinchuk, Arun Gunda · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2007
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets