Fault analysis on two-level (K+1)-valued logic circuits
Hui Min Wang, Chung Len Lee, Jie Chen · 2003
A general form and a set of basic gates in implementing two-level (K+1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K+1)-valued logic circuit, faults can be reduced to 19% of the original total faults.>