Simplifying SoC design with the customizable control processor platform
Clarence Rosser Ogilvie, Robert Ray, Robert Devins, Mark Kautzman, M. Hale, Reinaldo A. Bergamaschi, Bill Lynch, S.P. Gaur · 2004
We describe the customizable control processor (CCP) platform based on PowerPC/spl reg/ 440 processor with a target frequency of 533 MHz as well as its design methodology. The hardened region of the chip contains cores and features found in many control and communications applications. The custom area of the chip allows for each application of CCP to be personalized with cores from the IBM core library or with unique logic implemented in IBM ASIC standard cell. A predefined logic template (customer logic file) with a set of standard CoreConnect/spl reg/ ports can be personalized with any function that can be implemented in the IBM ASIC technology. The customer logic file is synthesized placed and wired in the custom area of the chip. The custom area of the chip could be configured with approximately 2 M gates of logic. With all mask levels being personalized other configurations could include SRAM, and embedded DRAM incorporated in the custom logic. There are around 263 pre-assigned I/O for the hardened portion of the chip as well as around 177 I/O sockets available in the custom region to personalize. The CCP provides a flexible platform and design environment that effectively reduces the design effort, design time, and the design cost of systems on chip.