SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division
M. Kovac, Nagarajan Ranganathan, Murali R. Varanasi · 2005
In this paper, we present a new VLSI chip for computing multiplication and division in Galois Fields GF(2m), for values of m 1. 8. The chip is based on a syslolic architecture which can produce a new result every clock cycle and the two operations can be interleaved. A prototype CMOS VLSI chip was designed, fabricated and tested. The chip was tested to be fully functional at 33.3 MHz.