Gate model networks for minimization of multiple-valued logic functions
Yutaka Hata, Takahiro Hozumi, K. Yamato · 2002
The use of gate model networks as a logic minimization method for multiple-valued logic functions is proposed. The gate model network is a kind of neural network constructed like and AND-OR two-level circuits using two gate models: an AND type gate model and an OR type gate model. The backpropagation (BP) method is used to train the network until it realizes the minimal solution. A solution is derived from the weights and thresholds. The gate model networks are applied to binary AND-OR circuit minimization and to the multiple-value max-of-min's expression minimization. It is shown that the gate model network is also applicable to minimize multiple-valued sum-of-products expressions, where sum refers to TSUM.>