On-line error detection techniques for dependable embedded processors with high complexity
M. Pfanz, Karsten Walther, H.T. Vierhaus · 2002
Presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the cross-parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors.