Energy-secure computing
Pradip Kumar Bose · 2012
The "power wall" has forced chip and system architects to design with smaller margins between nominal and worst-case operating points. Localized hot spots and temperature gradients exacerbate lifetime reliability problems. Smaller voltage margins make processors more vulnerable to inductive noise on the voltage rails, as well as soft errors induced by high energy particle incidence. The problem of process variation presents another obstacle to sustained performance growth in the late CMOS design era. At the same time, the emerging phase change memory (a promising technology for future low power, dense storage in systems) is vulnerable to malicious attacks that can reduce the lifetime of an already wear-out prone technology. These issues have all led to R&D in "better than worst-case" design principles. Dynamic power and thermal management control loops have already become an integral part of chip and system design. New research in wearout and general reliability management have recently been published. These new generation management protocols have, however, opened up other sources of concern: e.g. potential security holes exposed by the integrated control loops and system safety issues triggered by potential violations of power or thermal limits imposed by the original specification. We coin the term "Energy-Secure System Architectures" to cover the range of research being pursued within industry and academia in order to ensure robust and secure functionality, while meeting the energy-related constraints of the emerging "green computing" era. This keynote speech attempts to provide a summary overview of the problem and solution spaces around the theme of energy-secure computing -- with a special focus on servers and extreme-scale systems.