An FPGA-Based Parallel Distributed Arithmetic Implementation of the 1-D Discrete Wavelet Transform
Ali Al‐Haj · 2005
The fine grained parallelism inherent in Field Programmable Gate Arrays (FPGAs) may be well exploited to implement the computation-intensive discrete wavelet transform, which is increasingly employed in multimedia consumer electronics. In this paper, we describe a parallel implementation of the discrete wavelet transform and its inverse using Virtex FPGAs. We make maximal utilization of the look-up table architecture of the Virtex FPGAs by reformulating the wavelet computation in accordance with the parallel distributed arithmetic algorithm. The reported single chip implementation may be used effectively in the construction of low-power, wavelet-based MPEG-4 and JPEG2000 decoders.