3-valued trace-based fault simulation of synchronous sequential circuits
O.Y. Song, Prem R. Menon · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993
An efficient fault simulation algorithm for synchronous sequential circuits is presented. It uses parallel fault simulation with dynamic fault grouping, and combines it with backtracing within certain fanout-free regions and the use of surrogate faults. A backtracing method is developed to handle the three logic values, 0,1, and X, accurately. The concept of surrogate faults is also extended to represent all nine combinations of fault-free and faulty values. The results of simulating a set of benchmark sequential circuits show that reductions in execution time of 7-54% were obtained by the use of backtracing and surrogate faults compared to the well-known method, PROOFS.>