Recognition of logic diagrams by identifying loops and rectilinear polylines
S.H. Kim, Jung-Yul Suh, J.H. Kim · 2002
Proposed is a system that recognizes logic symbols and their interconnections on logic diagrams. The input diagram, digitized by scanner, is converted into a set of line segments through a sequence of picture processing operations. Then symbols and connections are extracted by identifying loops and rectilinear polylines utilizing a model-base in which symbols are graphically described. Experiment with a number of logic diagrams shows that the system correctly recognizes more than 96% of logic symbols and connections on an A4-size diagram with an average complexity within 15 s on a workstation.>