An implementation of scoreboarding mechanism for ARM-based SMT processor
Chang-Yong Heo, Kyu-Baik Choi, Inpyo Hong, Yong-Surk Lee · 2003
A SMT architecture uses TLP (Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processor, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme. The SMT architecture which has an in-order-issue scheme can use a simple issue mechanism with a scoreboard array instead of using register renaming or a reorder buffer. However, a SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper presents a simple but effective implementation of a scoreboard array for the ARM-based SMT processor.