Design of on-line division unit
P.K. Tu, M.D. Ercegovac · 2003
A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.>