Design and implementation of an ordered memory access architecture
Sharath Sriram, Edward A. Lee · IEEE International Conference on Acoustics Speech and Signal Processing · 1993
The authors describe a multiprocessor machine for real-time digital signal processing that uses commercial programmable DSP chips. The architecture is a shared memory, single shared bus parallel processor designed to run signal processing tasks that can be statically scheduled. The design is based on the architecture proposed by J.C. Bier and the authors (1990). A prototype has been built. The implementation details and performance results are discussed.>