UVM based testbench architecture for unit verification
Juan Francesconi, Juan Agustin Rodriguez, Pedro Marcelo Julian · 2014
In this work, the Universal Verification Methodology (UVM) is analyzed through its application in the development of two testbenches for unit verification. The first one targets a First Input-First Output (FIFO) buffer module and employs all the basic UVM components; a scoreboard with a Reference Model and a Functional Coverage collector are also implemented. The second one verifies an I2C EEPROM slave module; a bus functional model for the I2C protocol is defined to facilitate the driver implementation, rising the level of abstraction and allowing the reuse of the verification component for other I2C devices.