Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance
N. Venkateswaran, Arrvindh Shriraman, Niranjan Kumar Soundararajan · 2005
The MIP S.C.O.C was designed to overcome the Von-Neumann bottleneck and develop massive on-chip parallelism to achieve Teraflop scale single chip performance. We case study here a specific 2 MB MIP node that has a 128 bit datapath. This paper also specifies the technological reqirements and discusses the implementation strategy to support the feasibility of the project. We develop the ISA format and preview the hardware compiler COS, that will map applications and schedule the instructions on the MIP S. C. O. C. We then discuss the library specifications and COS-HLF unit interface. We develop the scalable pyramid cluster to accomodate massive node performance. We discuss briefly the programming model and an application execution to demonstrate the scalability.