A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system
Satoshi Kumaki, Hiroyuki Takata, Yoshiaki Ajioka, Tsukasa Ooishi, K. Ishihara, A. Hanami, Taizo Tsuji, Y. Kanehira, Takahiro Watanabe, Chikayoshi Morishima, Tomoaki YOSHIZAWA, Hisayasu SATO, Shinnosuke Hattori, A. Koshio, K. Tsukamoto, Takeshi Matsumura · 2002
A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.