IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH
P. Thorel, J.-L. Rainard, A. Botta, A. Chemarin, Jacques Majos · 2005
&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.