Optimization and Implementation of H.264 Encoder on Symmetric Multi-processor Platform
Ouyang Kun, Qing Ouyang, Zhengda Zhou · 2009
The H.264 video coding standard has achieved a significant improvement in coding efficiency over previous standards. However, the computational complexity of the H.264 encoder is increased drastically, which results practical difficulties in its implementation on the embedded platform. This paper presents two implementation techniques to optimize the H.264 encoder on the embedded symmetric multiprocessor architecture. We propose a coarse-grained functional partitioning method to balance the load of the encoder among the cores with small overhead of synchronization. On the other hand, we present a memory management optimization method to exploit the memory subsystem on the embedded platform effectively for the H.264 encoder. The experimental results demonstrate that, for the video sequences with VGA format, the performance of the optimized H.264 encoder is greatly improved.