1.0 Gbps LVDS transceiver design for LCD panels
Chua‐Chin Wang, Jianming Huang, Jih‐Fon Huang · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
LVDS has become a popular choice for high-speed serial links in large-sized display units. This work presents the design and implementation of I/O interface circuits for Gbps operation which is fully complied with the IEEE STD. 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. A CMFB (common mode feedback) circuitry is utilized in the transmitter to stabilize the common mode voltage in a predefined range. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver. A typical 0.25 /spl mu/m 1P5M CMOS technology is used to realize the proposed LVDS transceiver. The post-layout simulation reveals that the data rate is 1.0 Gbps at all process corners.