Enhancement of Clock Delay Faults Testing
Yoshinobu Higami, Hiroshi Takahashi, Shinya Kobayashi, Kewal K. Saluja · 2011
This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.