Test pattern generation for column compression multiplier
Pingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng · 2002
When used as the building cell of a parallel multiplier, the (4,2) counter tree is better suited than a Wallace tree for a VLSI implementation because of its more regular structure. In this paper test pattern generation for the CC multipliers is presented following a brief introduction to the structure of the (4,2) counter and the column compression multiplier using a (4,2) counter as its building cell. In conclusion, less test patterns are enough to exhaustively test the CC multiplier.