A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions
R. Rogenmoser, Leo H. O'Donnell, Shohei Nishimoto · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003
A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.