Test Pattern Generation of Relaxed $n$-Detect Test Sets
Stelios Neophytou, Maria K. Michael · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2011
While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detect orn-detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect (n-detect) test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact,n-detect test sets can be significantly reduced without any impact on then-detect property. Additionally, in many cases, the size of the test set is reduced.