Valid clocking in wavepipelined circuits
William K. C. Lam, Robert K. Brayton, Alberto Luigi Sangiovanni-Vincentelli · International Conference on Computer Aided Design · 1992
In thispaper, we conskier the problemof clocking wavepipelined circuits. Wavepipelined circuits can operate at a much higher clock rate than conventional pipelined circuits, because its maximum rate is limited only by the path delay difference instead of the maximum path delay, [Cot69]. Current research in this area has focused on minimizing the path delay difference, hence maximizing the achievable clockfrequency. In this paper, we present an analysis of valid clock rates in wavepipelined circuits using a technique called Timed Boolean Functions. We show that the valid intervals for the clock period can be disconnected. Thus, it is insufslcient to only know the minimum valid clock period in guaranteeing proper operation of pipelined circuits. We provide analytic expressions for the valid clock intervals in terms of both topological delay as well as 2-vector longest and shortest delays. Also uncertainties arising from manufacturing are taken into account. We also illustrate some potential dimulties in computing the exact valid clock intervals by demonstrating discontinuity and non-monotonicity of the harmonic number H (r) (the number of valid simultaneous data waves allowed) as a+tion of the clock period r.