Parallel implementation of transform-based DCT filter-bank for video communications
C.T. Chiu · IEEE Transactions on Consumer Electronics · 1994
This paper proposes a new filter bank structure based on the discrete cosine transform (DCT) and inverse DCT (IDCT) using modified autoregressive filter realization for real-time applications. The number of multipliers required in the synthesis bank is only N-1, which is the minimum number of multipliers for the IDCT compared to previous architectures. The VLSI implementations of the filter modules show that it can achieve 116 Mb/s and 540 Mb/s data rate under 2 /spl mu/m and 0.8 /spl mu/m CMOS SPDM technology.>