Random pattern testable logic synthesis
Chen-Huan Chiang, Sandeep K. Gupta · 1994
Previous procedures for synthesis of testable logic guarantee that all faults in the synthesized circuits are detectable. However, the detectability of many faults in these circuits can be very low leading to poor random pattern testability. A new procedure toperform logic synthesis that synthesizes random pattern testable multilevel circuits is proposed. Experimental results show that the circuits synthesized bytheproposed procedure tstfx are signi cantly more random pattern testable and smaller than those synthesized using its counterpart fast extract (fx) in SIS. The proposed synthesis procedure designs circuits that require only simple random pattern generators in built-in self-test, thereby obviating the need for complex BIST circuitry.